해석 자동화 시스템 개발

   

[Design Data Input]

 

1 EDIF – Schematic (Cadence direct input)

 

2 ODB - Package(.mcm), PCB(.brd)

 



   




[Pre-Process]

 

- Design data translation

 

1 EDIF - None

 

2 ODB

  - Design data healing

      - trace alignment, planes unification, remove invalid small hole

  - Net pre-processing

      - net grouping, net extension(PWR/GND, Signal)

  - Stack-up define

      - layer thickness, material properties

  - Setup

      - simulation setup, model assign, design rule parameter

 

- Running input file generation



   



[Run]

 

1 EDIF

  - Component stress & Design guide check

 

 

2 ODB

  - Simulation

      - Modeling : Spice subckt, s-parameter

      - Signal : TDR, DDR, SERDES, Single ended, Differential

      - Power : Plane Zo, Decap optimization

      - EMI : Near field, Far field

  - Design rule check

  - Design for Manufacturing



   




[Post-process]

 

1 EDIF - None

 

 

2 ODB

  - Simulation

      - Modeling : Reduced Matrix, Spice/S-parameter model generation

      - Signal : Waveform, Eye diagram, Timing margin analysis

      - Power : Impedance limit check, Recommended decaps set

      - EMI : Radiation limit check

  - Design rule check - None

  - Design for Manufacturing - None



 




[View]

 

- Result View

-

- User Comments for Report

-

- Select Results for Report

 
 



[Report]

 

  - Document Generation (.pdf/.xlsx)

  


Proposal Example

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